1. Field of the Invention
The present invention relates to an analog-to-digital converter and an analog-to-digital conversion method in which a supply current can be controlled corresponding to a sampling frequency.
2. Description of the Related Art
With an increasing demand for low power consumption in a digital apparatus (for example, thin television such as liquid crystal television and plasma display television) having an analog-to-digital converter mounted thereon, it is required to reduce power consumption in the analog-to-digital converter.
Meanwhile, the analog-to-digital converter is required to handle a variety of sampling frequencies, which influence the power consumption of the converter. The higher the sampling frequency is, the greater the consumption current becomes, and accordingly, the larger the power consumption becomes. Therefore, in designing an analog-to-digital converter adapted for a required sampling frequency, the analog-to-digital converter has to be designed individually for each sampling frequency, because an operating current value differs with each sampling frequency. This produces an increased development cost.
In contrast, there is another type of analog-to-digital converter capable of handling a plurality of variable sampling frequencies. When the current value is fixed in the analog-to-digital converter of this type, the supply current value has to be set to a current value (the maximum current value) with which the analog-to-digital converter is operable at the highest sampling frequency. As a result, when the analog-to-digital converter is operated at a lower sampling frequency than the highest sampling frequency, electric current is wasted because the current value remains constant (i.e. the maximum current value) although the analog-to-digital converter can be operated at a lower current value (operable current value) than the supplied current value. Namely, an electric current for the difference between the maximum current value and the operable current value is wasted.
Accordingly, it has been desired to develop an analog-to-digital converter to which an optimal operating current is supplied depending on a sampling frequency.
Meanwhile, in the official gazette of the Japanese Unexamined Patent Publication No. 2001-196929 (which is referred to as patent document 1), there is disclosed an analog-to-digital converter of which supply current is variably controlled, depending on a sampling frequency of a clock signal generated by a PLL (phase locked loop) circuit.
According to the above patent document 1, a bias circuit for supplying the electric current is controlled using an output signal from the PLL circuit generating the clock signal. In other words, when the PLL circuit is not used as the clock signal generation means, the method disclosed in the above patent document 1 is not applicable. In particular, when it is required to employ a highly accurate clock signal with an extremely small jitter, it may be considered to supply the clock signal from an oscillator circuit using, for example, a crystal oscillator, in place of the PLL circuit.